By Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu
This booklet offers a accomplished survey of modern development within the layout and implementation of Networks-on-Chip. It addresses a large spectrum of on-chip verbal exchange difficulties, starting from actual, community, to program layers. particular issues which are explored intimately comprise packet routing, source arbitration, blunders control/correction, program mapping, and conversation scheduling. also, a singular bi-directional communique channel NoC (BiNoC) structure is defined, with distinctive clarification.
- Written for training engineers short of functional wisdom in regards to the layout and implementation of networks-on-chip;
- Includes tutorial-like information to introduce readers to a various diversity of NoC designs, in addition to in-depth research for designers with NoC event to discover complex concerns;
- Describes various on-chip conversation architectures, together with a unique bi-directional conversation channel NoC.
From the Foreword:
Overall this publication exhibits very important advances over the cutting-edge that may have an effect on destiny process layout in addition to R&D in instruments and techniques for NoC layout. It represents a huge reference aspect for either designers and digital layout automation researchers and developers.
--Giovanni De Micheli
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Additional resources for Reconfigurable networks-on-chip
M. Daneshtalab, A. A. Kusha, A. Sobhani, Z. Navabi, M. D. Mottaghi, and O. Fatemi, ‘‘Ant Colony Based Routing Architecture for Minimizing Hot Spots in NOCs,’’ in Proceedings of the Annual Symposium on Integrated Circuits and System Design, pp. 56–61, September 2006 11. J. Hu and R. Marculescu, ‘‘DyAD–Smart Routing for Networks-on-Chip,’’ in Proceedings of the Design Automation Conference, pp. 260–263, June 2004 12. C. J. M. Ni, ‘‘The Turn Model for Adaptive Routing,’’ Journal of ACM, vol. 41, no.
Fig. 0235 Max. packet injection rate (packets/cycle/node) Fig. 5 Performance Evaluation Comprehensive simulations were run in Register Transfer Level using Cadence NC-Verilog. Performance metrics were carried out on an (8 9 8) mesh network. Each link bandwidth was set to one flit per cycle. Packets were generated and received by a host model attached to Port 0 of each router. In different evaluations, the sizes of buffers were configured in 16 and 32 flits, respectively; the size of packets was randomly distributed between 4 and 16 flits in all simulations.
S. Chatha, ‘‘Quality-of-Service and Error Control Techniques for Network-on-Chip Architecture,’’ in Proceedings of the Great Lakes Symposium on VLSI, pp. 45–50, April 2004 31. E. Rijpkema, K. G. W. Goossens, A. Radulescu, J. Dielissen, J. V. Meerbergen, P. Wielage, and E. Waterlander, ‘‘Trade-offs in the Design of a Router with Both Guaranteed and BestEffort Services for Networks-on-Chip,’’ in Proceedings of the Design Automation and Test in Europe Conference, pp. 350–355, March 2003 32. M. D. Harmanci, N.
Reconfigurable networks-on-chip by Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu